Deep analysis of ADC testing techniques in SOC

The ADC static test method has been studied for many years. There are standard test methods in the world, but the static test can not reflect the dynamic characteristics of the ADC. Therefore, it is necessary to study the dynamic test method. The dynamic characteristics include many, such as signal-to-noise ratio (SNR), signal. Ratio to noise + distortion (SINAD), total harmonic distortion (THD), spurious free dynamic range (SFDR), two-tone intermodulation distortion (TTIMD), etc. This paper discusses the digital signal method for the signal-to-noise ratio of the ADC. Test, calculate the effective number of bits, and test to prove that increasing the sampling frequency can improve the SNR, which is equivalent to increasing the effective number of ADCs. In this system, the AD9224 is used, which is a 12-bit, 40MSPS, single 5V power supply pipeline type. Low power ADC.

With the development of design and manufacturing technology, integrated circuit design has evolved from transistor integration to logic gate integration, and now it has evolved to IP integration. In recent years, it has developed into a system-on-chip phase, and SOC design technology has become one of the design hotspots. The design pattern of SOC is different from the vertical design mode of large-scale integrated circuits in the past. Its design pattern is horizontal, that is, the SOC integrator chooses the IP core provided by different vendors to build the chip system. This horizontal design pattern shortens the SOC design cycle on the one hand, and makes SOC testing a huge challenge on the other. The diversity of the IP core brings the complexity of the test. In terms of the design form of the IP core, there are three kinds of soft core, solid core and hard core; in terms of circuit type, there are digital logic core, memory core, analog/mixing Core; in terms of function, there are processor core, DSP core, multimedia core, etc.; in terms of circuit testability design method, there is built-in self-test (Built-in-Self-Test, BIST), scan test, boundary Scan test, test point insertion, etc.; as far as the clock is concerned, there are IP cores such as processor cores and DSP cores that require high-frequency clocks, and IP cores that only require low-frequency clocks such as peripheral controllers. SOC testing must consider support for diversity. Test resources are limited, the number of test channels that external test equipment can provide, the test channel depth and test time of ATE (AutomaTIc Test Equipment), and the simulated test components are all “scarce resources”. Therefore, the SOC test must consider all the details related to this.

2.1 IP/core test of analog/hybrid circuits

The test technology of the analog/hybrid circuit core is still immature. The AutomaTIc Test Pattern GeneraTIon (ATPG), which is widely used in digital logic circuits, cannot be simply transplanted into analog circuits. This is because: First, the time and value of the analog circuit waveform are continuous. The circuit function depends on the circuit topology and the parameter values ​​of the components. The dynamic range of the circuit parameters is large, and it is difficult to establish a fault model. Second, the analog signal is Continuous quantities, whether passing the test stimulus from the original input or the test response from the circuit under test, these values ​​may be changed during the transmission; third, due to the continuity of the analog signal, the measurement error is easy to cause Misjudgment. In order to improve the testability of the circuit, in order to improve the testability of the circuit, three techniques are often used: First, the functional structure is reorganized. This method uses the functional structure of the circuit to be reorganized and is different from the normal working mode, and uses the output signal to discriminate. Whether the circuit has an error. The typical method is crystal oscillator test, which generates an oscillating signal of a certain frequency. The fault circuit changes the frequency of the oscillating signal, and an error is observed by monitoring the change of the signal frequency. Second, insert a test point, such as adding a current sensor to the circuit. A faulty circuit changes the current and observes the error. Third, performing digital-to-analog/analog-to-digital conversion, that is, adding an analog-to-digital converter and a digital-to-analog converter to the chip design, turning the analog output signal of the circuit to be tested into a digital signal, and turning the digital input signal of the circuit to be tested into Analog signals to achieve excitation and response propagation.

2.2 ADC test method

2.2.1 Test Adapter Design Techniques

The test adapter is the key to the connection between the chip and the tester. Pay special attention to the layout and routing method in the design to minimize the introduction of noise: the ADC is between the analog circuit and the digital circuit, and is usually classified as an analog circuit. In order to reduce the interference of the digital circuit, the analog circuit and the digital circuit are arranged separately inside the chip; in order to reduce the distributed resistance, capacitance and inductance on the signal line, the length of the wire is shortened and the distance between the wires is increased. To reduce the impedance of the power and ground wires, increase the width of the power and ground wires as much as possible, or use the power plane and ground plane. Similarly, the ground plane of the analog circuit should be separated from the ground plane of the digital circuit, and the impedance matching should be considered. If it is a differential input, the wiring method of the differential pair should be considered, so that it is ideal to test the dynamic parameters and static parameters of the ADC. .

2.2.2 Test Instance

2.2.2.1 Device characteristics

The test chip in this paper is a SOC chip with a 10-bit high-speed AD converter module. The characteristics of the ADC module are as follows:

1) Power supply 4, analog power supply 1, 2 (3.3V, 1.8V).

2) With a pair of differential inputs, the common mode voltage is 1.5V and Vp-p is 1V.

3) The digital clock frequency is 50 MHz, the sampling frequency is 25 MHz, and the input wave frequency is 2 MHz to 36 MHz.

This ADC was tested using Agilent's SOC 93000 test system. Since the chip has a pair of differential inputs with a common-mode voltage of 1.5 V and Vp-p of 1V, this means that the analog input voltage range is 1 to 2V. The analog input accuracy is this:

In order to test chips with such precision, we need to input analog voltages with higher precision. The accuracy of the analog voltage input during this test is:

In order to produce such a high-precision analog voltage signal (with a voltage accuracy of about 200μV) during the test, the roadband High Speed ​​AWG (500MHZ Sample/s 12-bit) test hardware was used. The specific performance indicators of the AWG are shown in Table 1.

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