Design of CCD Video Signal Processing Circuit Based on XRD4460
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Abstract : This paper introduces the function and characteristics of the dedicated CCD video signal processing chip XRD4460, and uses the chip to design a CCD video signal processing circuit, and gives its detailed hardware and software design. The circuit is suitable for signal processing in a CCD camera, and has a simple structure, high reliability, stable performance, and has broad application prospects. Key words : CCD; correlated double sampling; gain control; signal processing1 Introduction
CCD (Charge Coupled Device) is a new type of semiconductor large-scale integrated optoelectronic device developed in the 1970s. Because it has unique features in image information acquisition and recording, and has many advantages such as small size, low power consumption, high resolution, high sensitivity, and good reliability, it has a wide range in science, astronomy, industry and other fields. application.
The video signal output by the CCD includes a high DC component and noise in addition to a useful image signal. If it is not processed, it will seriously affect the image quality of the sensor, so the noise processing of the CCD video signal is very important. The purpose of CCD video signal processing is to eliminate all kinds of noise and interference as much as possible, but not to lose image details; and to ensure that the image signal changes linearly with the target brightness within the dynamic range of the CCD, and at the same time, for computer processing and large capacity. For storage, the CCD output signal must also be digitized [1] . If these functions are implemented by discrete circuits, the disadvantages of complicated circuit, inconvenient debugging, high price, and high power consumption are obvious. This is more powerful, more perfect, cheaper, and lower power consumption than CCD cameras. The development trend is contrary. With the development of microelectronics technology, in order to solve the problem of CCD video signal noise processing, many companies (Exar, Kodak, Burr-Brown, TI, etc.) have developed a full-featured dedicated CCD video signal processing chip to integrate various functional circuits. On a chip, this not only greatly simplifies the signal processing circuit, reduces the design complexity of the CCD camera, but also makes the CCD camera more powerful and superior in performance.
This paper mainly analyzes the function and characteristics of the dedicated CCD video signal processing chip XRD4460, and designs the CCD video signal processing circuit based on XRD4460.
2 Features and functions of XRD4460
The XRD4460 is a dedicated CCD video signal processing chip from Exar. It belt
There is a 1O bit A/D converter with a maximum sampling rate of up to 16MHz, a high-bandwidth differential correlation double sampler (CDS) and an 8-bit digitally programmable gain amplifier (PGA). Analog offset controllable, differential signal input, differential external clock, on-chip with input buffer and sample/hold, 1O bit parallel data output. Due to its powerful functions, superior performance, low power consumption and small size, it is widely used in digital imaging systems such as digital cameras, digital still cameras and PC video conferencing cameras. The functional block diagram of the XRD4460 is shown in Figure 1. Its functions mainly include.
( 1 ) Correlated double sampling ( CDS , correlated double sampling ): The main CCD output signal is photon noise, trap noise, dark current noise, and reset noise. Among them, photon noise and trap noise are caused by devices and processes, which are difficult to handle, and dark current noise is related to the ambient temperature of the device. Therefore, the signal processing circuit mainly suppresses reset noise (also known as KTC noise) [2] . To reduce reset noise, the XRD4460 uses a correlated double sampling technique. The principle of correlated double sampling is that the reset noise appears to be approximately constant (ie, has correlation) in the same pixel period, but is randomly varied for different pixel periods. Therefore, as long as the dark level reference interval and the signal level interval in the same pixel period are sampled twice, the reset noise of the two samples is correlated, and the two sampling levels are output through the differential amplifier. The signal is the real video signal. This process filters out the reset noise associated with both the reference level and the signal level, and also has a certain filtering effect on low frequency noise [3] .
( 2 ) Programmable gain control PGA (programmable gain amplifier) : The voltage of the video signal input to the ADC is determined by the voltage of the CCD output signal and the system gain and offset of the signal processing. Because the size of the CCD output signal changes with the intensity of the incident illuminance, it can only be adjusted by gain and offset through the signal processing system. In order to meet the requirements of the brightness and contrast of the output digital image. The gain control of the XRD4460 is accomplished by a programmable gain amplifier, PGA, with a gain range of 6dB to 38dB, controlled by an 8-bit gain register, and set via the serial port. When the input gain code Code=00H, the system has an inherent 6dB gain. For each codeword added by the gain control code, the system gain is increased by 0.125dB to achieve programmable gain control.
( 3 ) Dark level automatic correction: due to the light intensity, temperature, and the slow change of the power supply voltage, the dark reference level of the video output signal will fluctuate. In practical applications, the dark reference power is required to maintain a fixed level, dark. The reference level correction process is also the DC level recovery process. In this case, several dark level reference pixels are distributed at the beginning or end of the CCD output video signal. The XRD4460 corresponds to the dark reference pixel of the output signal by the high level of the CLAMP signal. Selecting the appropriate external coupling capacitance parameter will keep the dark reference level of the entire line at a fixed level.
( 4 ) Digital bias control: If the CCD is operated under low light conditions, even if the gain of the signal is large, the voltage after the video signal processing may still be lower than the lower reference voltage of the ADC, which causes distortion of the output video image. In order to improve the grayscale resolution under low light conditions, it is necessary to make the dark reference level of the output video signal higher than the lower reference voltage of the ADC. Therefore, it is not enough to adjust the gain only, and the offset of the video output signal needs to be adjusted. The offset adjustment of the XRD4460 is also controlled by the serial port to control the on-chip 8-bit bias register. The default offset setting value is 08H after the power is turned on, and the offset adjustment range is 02H to 08H.
(5) A/D analog-to-digital conversion: The XRD4460 integrates a 10-bit resolution, successive comparison A/D converter. Due to the principle of binary search, the conversion rate is up to 16MHz. This conversion speed and conversion accuracy are suitable for Most applications.
(6) Serial interface: The serial interface of XRD4460 includes a 10-bit shift register and multiple parallel registers. It controls the writing of internal registers through three signals of LOAD, SDI and SCLK to realize the programming of XRD4460 working parameters. control.
3 CCD video signal processing circuit hardware design
The CCD video signal processing circuit takes the dedicated CCD video signal processing chip XRD4460 as the core component, completes the amplification, noise processing and digitization of the CCD video signal, and uses CPLD (Programmable Logic Device) technology to complete the logic control of the whole circuit, with advanced first The output (FIFO) memory acts as a data cache for storing AD-converted data and uses a USB interface chip with a microcontroller to input CCD data into the computer via the USB interface. The CCD video signal processing circuit design is shown in Figure 2. It can be roughly divided into three parts.
3.1 XRD4460 video signal processing circuit
The working sequence of the XRD4460 dedicated CCD video signal processing chip needs to be determined according to the specific CCD chip. In Figure 2, the SHD, SHP, RST, and CLAMP signals must be designed based on the timing of the CCD output signal. Its timing relationship is shown in Figure 3. The CCD output signal is processed by the CCD signal processor XRD4460, that is, subjected to double correlation sampling (CDS) denoising processing, then subjected to gain amplification and offset adjustment, and then subjected to A/D conversion to obtain 10-bit digital data. These data are stored in the asynchronous FIFO memory SN74V293 under the control of the CPLD logic control circuit. SDI, SCLK, and LOAD are the serial port control signals of the XRD4460. The serial interface makes it easy to programmatically control the gain and offset adjustment of the XRD4460 to improve the quality of the output image.
3.2 FIFO and USB interface circuit
High-speed A/D conversion data cannot be directly sent to the host via USB, and data needs to be buffered through the FIFO. The circuit uses TI's SN74V293 chip. Its capacity is 65536×18 or 131072×9, and the fastest read/write period is 6 ns, which can satisfy the storage of 100MHz sampled data. When the input and output width of the SN74V293 is set to 18 bits, it can store 64K × 10 bits of data. The timing relationship between the FIFO write clock W and the reset signal /RS is as shown in FIG. The USB interface circuit adopts Cypress's EZ-USB chip CY7C68013A, which has USB2.0 transceiver, serial interface engine SIE (Serial Interface Engine), enhanced 8051 core with 16K, 4KB FIFO memory and general programmable interface GPIF. The (General Programmable Interface) is integrated into the main control chip of the USB external device, and the USB chip communication initialization and communication connection with the host can be realized without an external microcontroller (MCU). When data is stored in the FIFO, the USB interface circuit reads the data according to its flag signal (full signal / half full signal) and sends it to the host.
Figure 4 FIFO write control timing
3.3 CPLD logic control circuit
The logic control circuit is implemented by the CPLD using the VHDL hardware description language to complete the logic control of the whole circuit, mainly including three parts of functions. The first part of the function is to provide working timing for the XRD4460 (Figure 3). The second part of the function is to provide the write clock W and the reset signal /RS to the FIFO to control the smooth writing of the data. The third part of the function is responsible for the serial port settings of the XRD4460. Design a serial port and a register in the CPLD, where the serial port is used to send the data in the register to the XRD4460 for function setting; and the register is used to store the data sent by the host. The host sends data through the EP2 endpoint in CY7C68013A.
4 CCD video signal processing circuit software design
The USB application system software design is divided into three parts: the firmware of the USB peripheral (Firmware), the client driver on the host operating system, and the host application software. The host application software communicates with the system USBI (USB Device Interface) through the client driver, and the system generates USB data transfer actions; the firmware responds to various USB standard requests from the system to complete various data exchange work and event processing [ 4] .
4.1 USB interface programming
The firmware program is a control program of the microprocessor in the USB chip, and can be designed in assembly language or single-chip C language. When the system is powered up, the firmware is downloaded to the internal RAM of the CY7C68013A via a USB cable.
The firmware program is mainly to implement USB communication. When the host and the chip perform USB communication, an external interrupt 0 is generated, which is judged by the interrupt vector register. The three interrupts, Setup_packed_Int, Input_endpoint0_Int, and Output_endpoint0_Int, are mainly used to establish a connection with the host, perform control transfer or interrupt transmission; Input_endpoint1_Int, Output_endpoint1_Int are mainly used in bulk transfer. Different interrupt programs are executed in the firmware to implement USB data transfer. All interrupt handlers are written in C language.
4.2 host software design
First develop the driver for CY7C68013A in the host. The driver under Win2000 was developed with WinDK3.0, and the standard interface functions for control transfer, interrupt transfer and batch transfer were realized.
In application development, applications are written in VC++. Operate the USB device as a file, use CreateFile to get the USB handle, use DeviceIoControl to control the transfer, and use ReadFile and WriteFile for the bulk transfer. It mainly realizes two functions: one is to complete the display of the acquired image; the other is to set the CCD video signal processing chip, including the setting of working parameters such as PGA gain and ADC offset.
5 Conclusion
This paper introduces a CCD video signal processing circuit designed with dedicated CCD video signal processing chip and CPLD technology, and uses USB interface technology to realize data transmission. The circuit is not only simple in structure, but also easy to debug and easy to implement. The control of the dedicated CCD video signal processing chip through USB and CPLD technology realizes the programmable adjustment of image brightness and contrast, improves the image quality, improves the overall performance of the circuit, and the USB interface has a fast transfer rate and is easy to be computerized. connection. Therefore, the circuit can be widely applied to the design of a CCD camera system.
references
[1] Wang Qingyou Image Sensor Application Technology [M] Electronic Industry Press 2003
[2] Liu Guoyuan, Li Luyao, Zhang Bozhen, Bian Chuanping Application of CDS Device in TDI-CCD Video Signal Processing[J] Photonics Journal 2000 Vol.29(1) 82-85
[3] Zhai Shoufeng, Yan Jin, Hao Zhihang Research on CCD Image Sensor Noise Reduction Technology [J] Optics and Precision Engineering 2000, Vol.8(2): 140-145
[4] Feng Guofei, Song Yunxing Design and Implementation of USB Data Acquisition Card[J] Microcomputer Information 2005 21-1:75-76
[5] EXAR Corporation, Datasheet of XRD4460, 2004
[6] Cypress Semiconductor Corporation, CY7C68013A/CY768015A, EZ-USB FX2 USB Microcontroller, 2004.
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