This article is used to familiarize yourself with the use of Xilinx's Vivado HLS (2012.2 version) tool.
Since Zedboard is an ARM+FGPA architecture, it often involves knowledge about FPGA design when it is used. This is an insurmountable obstacle (at least for now) for people like me who don't know about FPGAs. I want to know about it, and then this piece of knowledge system is also very large, not clear in a short time. If you have a tool that can convert software code directly into hardware (HDL language) without having to learn traditional hardware design techniques, that's great! Here, Vivado HLS is such a tool.
This converts a piece of C code into an IPcore that the Xilinx EDK tool can use directly, implementing a simple 8-bit adder.
#include "basic.h"
#include "ap_interfaces.h" //define some macros for axi bus
Void basic(char a, char b, char *c) {
AP_INTERFACE_REG_AXI4_LITE(a, BUS_A, ap_none);
AP_INTERFACE_REG_AXI4_LITE(b, BUS_A, ap_none);
AP_INTERFACE_REG_AXI4_LITE(c, BUS_A, ap_none);
AP_CONTROL_BUS_AXI(BUS_A); // AP control signal to be accessed through AXI-Lite if
*c = a + b;
}
(1) IO Port
There are three variables in the function: a, b, c. The first two variables a, b are input variables, so they are the input ports of IPcore; the c variables are output variables, so they are the output ports of IPcore. They are mapped to the three registers in the core.
(2) Handshake signal
In this example, at least 3 control signals are required: AP_START, AP_IDEL, AP_DONE. These signals are also mapped into the core registers to control the basic operation and state of the core. The AP_START signal is used to control the start of the Pcore, the AP_DONE signal is used to indicate the completion of the operation, and the AP_DONE is used to indicate the idle state of the device.
(3) Interrupt control
The register associated with the interrupt. IER (intr enable reg), ISR (intr status reg)
(4) IPIF and IPIC
Here, the AXI-LITE interface is implemented by calling a macro in ap_interface.h.
// ap_interface.h - - this file contains macro declaraTIons for AutoESL interface direcTIves
// enum of available interfaces type in AUTOESL
Enum AP_AUTO_INTERFACES {
AP_NONE, AP_ACK, AP_VLD, AP_OVLD, AP_HS, AP_CTRL_NONE, AP_CTRL_HS, AP_MEM, AP_FIFO, AP_BUS
};
// GCC pre-processor direcTIve to insert pragmas from macro code
#define STR(x) #x
#define PRAGMA_L1(x) _Pragma(#x)
#define PRAGMA(x) PRAGMA_L1(x)
#define AP_INTERFACE (var_name, interface_type) { \
PRAGMA (AP interface interface_type port=var_name);
}
#defien AP_INTERFACE_REG (var_name, interface_type) { \
PRAGMA (AP interface interface_type port=var_name register ) ; \
}
// Create an AXI4 Lite interface at the system level layer
#define AP_BUS_AXI4_LITE (var_name, bus_name) { \
PRAGMA (AP resource core=AXI_SLAVE variable=var_name metadata=STR(-bus_bundle bus_name));
}
// Create standard Xilinx bus interfaces
#define AP_INTERFACE_REG_AXI4_LITE (var_name, bus_name, interface_type) { \
AP_INTERFACE_REG (var_name, interface_type); \ //IPIC
AP_BUS_AXI4_LITE (var_name, bus_name); \ // IPIF
}
// DeclaraTIon of a function control bus
#define AP_CONTROL_BUS_AXI (bus_name) { \
PRAGMA (AP resource core=AXI_SLAVE variable=return metadata=STR(-bus_bundle bus_name)
Port_map={{ap_start START} {ap_done DONE} {ap_idle IDLE} {ap_return RETURN}} );
}
Tool operation process:
(1) Create a new project
Crate new project -> Project Name and Location (no space allowed)-> Add source file -> Add test bench file
-> Solution Configuration -> Finish.
(2) C validation
Compile -> run
(3) High level Synthesize
(4) Design Optimization
(5) Implementaion (RTL Export)
The first time you do this step is probably wrong, and you don't know if it is a version.
Export is the time to make Format Selection, mainly:
Pcore for EDK
System Generator for DSP
IP-XACT
a) Format one, mainly to generate the RTL in the form of IPCore, and then use it in the EDK. In this experiment, we chose this method. For this format, Vivado HLS will be in the process of exporting
The ISE tool is called to synthesize the RTL logic, so the ISE's execution path must be added to the system environment variable. Otherwise, "@E [IMPL-28] Failed to generate IP" will occur.
b) Format 2, not used yet.
c) Format 3, mainly used for the use of EDA and ESL tools. For this export format, Vivado HSL will call Vivado to synthesize the RTL logic, so the Vivado execution path must be added to the system environment variable.
go with. Otherwise, "@E [IMPL-4] 'xtclsh' cannot be found. Please check your PATH variable."
For these two issues, see the official
At this point, the V code is converted to the FPGA code by Vivado HLS, and the interface is specified by the interface macro. The exported IPCore can be integrated with the processor in the EDK.
The generated IPCore is located in the ...\solutionx\impl\ directory.
At the same time, the include directory recorded in pcores\ipname_version\ includes a simple low-level driver and high-level driver for hardware devices. When in Standalone OS mode, the software code can directly use the API functions in this directory.
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