Nothing is to use the CPU as the main device of the system, or use FPGA as the main device of the system. The first problem to be considered in the system design is the startup loading problem of the processor. XILINX's ZYNQ scalable processing platform includes two high-performance ARM Cortex A9 hard cores (called processing systems (PS)) and FPGAs (called programmable logic programmable logic (PL)). The system design of the platform has great flexibility. In this paper, the ZYNQ system will encounter the startup loading problem as a description of the startup loading. If there is any inconvenience, please be a master. ^_^1. The device configuration unit ZYNQ devices all have a device configuration unit (device configuraTIon unit (DEVCFG)), which is controlled by the PS to provide initialization and configuration functions for PS and PL under software control. Previously, the download method provided by a single FPGA device is no longer applicable, and the configuration download of the PL must be performed with the participation of the PS. The Zynq-7000 device configuration unit includes the following PS units: 1CPU2OCM (boot ROM and shared RAM) 3 partial top-level bus and peripheral 4PS device configuration module on the PL side, the following units will also participate: 1PLS device configuration logic and interface 2 The decryption/authentication hardware 3 stores the decryption key in the eFUSE unit or the battery backup RAM (BBRAM). The figure below shows the PS device configuration subsystem block diagram: [[wysiwyg_imageupload:1338:]] provides the following key features: A. Three different PS configuration methods are available, including two main modes and one slave mode. 1 Encrypted Master Mode 2 Unencrypted Master Mode 3 Unencrypted Slave Mode B. 3 different main mode startup sources 1NOR FLASH2NAND FLASH3QSPI FLASHC: JTAG non-encrypted slave mode D: PS/PL encryption with AES-256 and HMAC (SHA-256) Download E: Master DMA interface for high-speed configuration F: 100 MHz 32-bit PCAP stream interface H: SoC encryption debugging function When the system is powered on reset, PS samples the dedicated bootstrapping signals pin level to determine the way to boot the device. This boot process is implemented by a Cortex A9 core executing the on-chip ROM code. The function of the ROM code is to initialize the L1 cache and the basic bus system, load the corresponding NAND, NOR, Quad-SPI, and PCAP drivers from the specified interface. Load the first stage BOOTLOADER (the first stage boot loader (FSBL)) to the on-chip execution. Due to the limited size of the OCM RAM, the first level BOOTLOADER size is up to 256KB. The user only needs to provide the boot image and set the correct bootstrapping signals pin level as required. When the system is powered on, the ROM code is automatically loaded into the chip and the program is transferred to the boot image. At this time, all the control functions of the system are handed over to the user. Boot image control, the second level BOOTLOADER function that the user wants to implement is implemented by the program that starts the image. For the encryption configuration method, the AES-256 decryption code and the SHA-256 signing (signature) algorithm are required. The PS needs to use the hard-wired AES-256 and SHA-256 modules in the PL, and the encryption configuration is required. The lower PL must be powered up, even if the system is not configured with the PL part. The device's encryption key can be selected by the user to be stored in the on-chip eFUSE unit (with power-down non-volatile) or internal battery-powered BBRAM (with power-down volatility, suitable for higher security requirements) ), the following table summarizes the configuration mode and related information: [[wysiwyg_imageupload:1339:]] Second, PS non-encrypted main mode configuration process This mode PS boot image is directly from external non-volatile memory (NAND, NOR, Quad -SPI) is loaded into the on-chip OCM, then the PL image can be directly configured into the PL. The whole process is as follows: [[wysiwyg_imageupload:1340:]] The configuration of the PL image can be implemented by the configuration interface module with DMA at high speed. The speed can reach 400MB/s in the case of non-encryption and 100MB/s in the case of encryption, which is very useful when the FPGA needs partial reconfiguration. Third, PS encryption main mode configuration process PS encryption main mode uses the bit and on-chip PL part of the hardware AES-256 decryption module and SHA-256 module to decrypt and integrity identification of the PS boot image, the device key is stored in the slice Within the eFUSE unit or internal BBRAM, after the PS is successfully loaded, the user can choose to configure the PL part with the following default PL boot process, as shown in the following figure: [[wysiwyg_imageupload:1341:]] where the bit stream is configured with PL It can be either a bit stream that has been encrypted by AES-256, or it can be sent to the PL as a plaintext bit stream after being decrypted by the PS first. The confidentiality of this process is selected by the user. If the PS integrity verification fails during the boot process of the secure ROM, the CPU immediately asserts the PROG_B signal and clears the PL content, and simultaneously issues an encrypted reset signal, which resets the internal RAM and registers of the PS, and then the CPU enters sleep mode, and the system only repeats Power on to reset. The PL configuration takes place in the second phase of the BOOT. This process can be configured one or more times at any time by the user's choice of his own method. It is not necessary to configure the PL part by the default PL boot process. Start Mode Pin The ZYNQ device has five start mode signals mode[4:0] to indicate where to start, whether it is JTAG mode, whether the PLL is bypassed, etc. In addition, two voltage mode signals vmode[1:0] are used to indicate the voltage mode of MIO BANK. The vmode[1:0] signal and the mode[4:0] signal are used to determine the level value by pull-up and pull-down. The pull-down resistor is recommended to be 20k ohms, the pull-up is connected to the VCCO_MIO0 voltage, and the pull-down is connected to ground. After the system releases the PS_POR_B reset pin, these startup mode pin signals are sampled by three PS_CLK clocks to determine the startup mode. The I/O pins corresponding to the vmode[1:0] signal and the mode[4:0] signal are MIO[8:2]. The specific meanings of each signal are as follows: 1Mode[0] is used to indicate whether it is JTAG positive. 2Mode[3:1] is used to select the startup source, whether it is from NOR Flash or NAND Flash or QSPI. 3Mode[4] is used to enable the PLL. 4Vmode[1:0] is used to configure the I/O BANK voltage. The correspondence between these signals and the MIO pins is as follows: [[wysiwyg_imageupload:1342:]] Note: X in the above table indicates no concern. In the actual design, the number of MIO pins is limited (only 54), and only two BANKs are divided (MIO Bank 0 corresponding pins are PS_MIO[15:0], PS_CLK, PS_POR_B; MIO Bank 1 corresponding pins are PS_MIO [53:16], PS_VREF_MIO and PS_SRST_B), it is not recommended that the system be designed to boot from parallel NOR Flash, because this way NOR Flash occupies a large number of MIO pins (greater than 40 pins), the system is designed to be from NAND Flash or QSPI can be started. These two methods use less MIO pins. The advantage of NAND Flash is that the capacity is relatively large. The disadvantage is that the read/write speed is slower (typical speed is 10MB/s). QSPI is also a kind. NOR Flash, but the interface is a four-wire serial interface, which can get a relatively high read and write speed (typical speed 50MB / s), if the system wants to start from other ways such as USB, Ethernet, SD / SDIO, etc., this requires users Start the boot code yourself in the first level boot image. The above is a good example. The main reference is Zynq-7000 Extensible Processing Platform Technical Reference Manual. You can download it on the official website of XILINX to study it carefully.
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