Portable positioning system solution based on SOPC technology
With the continuous improvement of GPS (Global PosiTIoning System) global positioning system, the application field is constantly expanding, and now it has spread to various sectors of the national economy, and has begun to gradually deepen people's daily lives. At present, the volume of products based on GPS positioning is generally large, and most of the processing cores use single-chip microcomputers and single-board machines. The product development cycle is long, the development cost is high, the product upgrade is inconvenient, and the life cycle is short.
The development of very large scale integrated circuit technology, especially the development of PLD and FPGA technology, makes it possible to implement the entire embedded system on a programmable chip. SOPC (System on a programmable chip) technology integrates modules necessary for system design such as CPU, memory, I/O interface, etc. on one FPGA. It has flexible design, can be reduced, expandable, upgradeable, and software and hardware can be programmed in the system. The function [1].
This paper designs a portable positioning system based on SOPC technology, and proposes a GPS/digital compass combined positioning solution for the problem that GPS is prone to locate blind spots in urban high-rise buildings and underground parking lots. This paper first introduces the system composition and hardware implementation, and then analyzes the software development in detail, and gives the source program. Finally, the test prototype is tested to verify the feasibility of the system.
1 system basic structure
The NIOSII-based portable combined positioning system consists of two parts: the receiving terminal and the monitoring center. The receiving terminal receives the GPS/digital compass combined positioning signal, and sends it to the monitoring center through the GPRS module, and the monitoring center performs data fusion on the received combined positioning signal, adopts a map matching method based on the fuzzy pattern recognition technology, and uses the GIS electronic map library. The high-precision road information is used as a classification template for pattern recognition, and the positioning accuracy of the GPS receiving data is improved according to the recognition result, real-time matching of the data with the electronic map is realized, and the position of the wearer of the receiving terminal is displayed in real time, and the authorized user can also pass The Internet can view the location of the terminal wearer anytime, anywhere. In the event of an emergency, the terminal wearer can trigger an alarm button on the terminal, which is processed in real time by the monitoring center.
2 receiving terminal hardware design
The system receiving terminal hardware consists of an FPGA chip and GPS module, GPRS module, digital compass module, alarm module, etc. In the FPGA chip, the functions of NIOSII soft core processor, on-chip memory and digital interface circuit are mainly realized.
NIOSII is a 32-bit RISC embedded processor from Altera that can be combined with user logic for programming into Altera FPGAs. The processor has a 32-bit instruction set, 32-bit data channel and configurable instruction and data buffering. The implementation cost is low. The implementation cost in FPGA is only 35 cents. It has high flexibility and adopts soft core form with complete customizable features. Designers can choose from a variety of system settings based on actual needs to achieve optimal performance, features and cost, with performance in excess of 200 DMIP [2]. It is very convenient to update by downloading the hardware configuration file to the FPGA.
According to the functional requirements of the system and the high configurability of the NIOS II soft core processor, the NIOS II soft core processor system customized in the hardware development tool SOPC Builde is shown in Figure 1. The NIOSII soft core is implemented on an Altera EP1C12Q240C8 FPGA. CPU, OnChip RAM, TImer, UART, Epcs controller and other modules, NIOSII soft core CPU and other IP modules are connected by Avalon on-chip bus, which specifies the port and communication timing of the connection between the main unit and the slave unit.
Figure 1 Customized NIOSII processor system
The UART serial communication module is used for NIOSII processor and external communication. The system collects the positioning signals of GPS and digital compass through the serial port, and sends the positioning signal and alarm signal to the GPRS module to the monitoring center through the serial port. On Chip RAM improves the on-chip memory cell for the system. The CY1C12Q240C8 provides 239,616 bits of RAM cells. The system does not need to expand the external memory. The Epcs controller module is used to download hardware configuration files and programs from the serial configuration chip to the FPGA when the system is powered up. The TImer timer module provides a system timer interrupt. The alarm module consists of a button. When the terminal wearer encounters an emergency, it will alarm the monitoring center through the trigger button. The power module provides system power to the system, and the crystal module provides the system clock to the system.
3 receiving terminal software implementation
The receiving terminal software development is carried out in the integrated development environment Nios II IDE, which mainly completes the collection of positioning data and communication with the monitoring center.
3.1 Software Development Environment Nios II IDE
Nios II IDE is the main development tool of Nios II soft core processor. It is based on open and extensible Eclipse platform. It provides a complete C/C++ design development environment for software development. It includes a project management and source code development. Based on the JTAG debugging function of the graphical user interface (GUI), HAL (Hardware AbstracTIon Layer, hardware abstraction layer) can use C language-like library functions to access hardware devices or files [3], shortening the software development cycle.
3.2 HAL system library
The HAL (Hardware Abstraction Layer) system library provides a simple device driver interface for embedded software developers to access the underlying hardware. The NIOS II soft core processor supports HAL, which provides the following support for users: integration with ANSI C Standard library - provides standard library functions like C; device drivers, which provide access to each device in the system; HAL API, provides standard interface programs such as device access, interrupt handling, etc; system initialization and device initialization, Initialization of the processor and system peripherals before the main() function is provided. The HAL-based system hierarchy is shown in Figure 2.
Figure 2 HAL-based system hierarchy
3.3 Receiving terminal software development
According to the function of the system, the software design flow chart is shown in 3.
Figure 3 software design flow chart
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