As the high-speed signal rate on the PCB increases, the high-speed design scheme introduces more DRCs into the PCB design. The most common ones are DRCs such as K/L and K/V. The designer allows the existence of these DRCs, but the proportion of these DRCs has exceeded 50% of the entire board DRC, their presence will reduce the running speed of ALLEGRO, and even extend the running time of certain operations (for example: update DRC, Database check Etc.) also affects the efficiency and quality of DRC inspection before boarding. The Via structure feature of Allegro 17.2 helps designers remove these DRCs, improving design efficiency and design quality.
Step 1: Create a Via structure as needed
Designers can create different Via structures according to their needs. Via structure can contain the design objects you need, such as Via, Shape (including RKO), Cline, etc. Via structure is very simple to create, find the following command, follow the prompts in the Command bar to complete successfully. Here are some examples we have, just to illustrate how to use them.
1. On the chip side of the Via structure example, the Via structure can be just Cline, or a composite of Via, shape, and Cline. The specific inclusion of the object is determined by the designer.
2. Sample of Via structure for high speed wiring layer switching.
3. Sample Via structure on the connector side. You can only include Cline and other objects you need.
Step 2: Call Via structure in the design
Once the Via structure is defined, we can call it directly in the design and then connect it to complete the routing of the high-speed link. In the following example, a high-speed link design was completed using several of the Via structure examples mentioned above. After the design is completed, errors such as K/L and K/V are no longer present, and the design becomes more effective and is more conducive to improving the design quality.
Allegro's Via structure feature helps designers eliminate the reasonable DRC introduced on the PCB to implement design requirements. Make the design more efficient, high quality, and promote the consistency of high-speed signal design (you can directly call the existing template every time you encounter a similar design).
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