Semiconductor giants push process development process 32nm chip close to practical
Following the guidance of Moore's Law, global semiconductor giants are moving toward 32-nanometer processes; however, their research and development strategies are different.
There are three camps for the development of microchip technology for 32nm chips worldwide. The largest number of participating companies is the IBM camp, followed by Intel Corporation, and the third is Japanese companies. In addition, TSMC in Taiwan and IMEC in Europe and Belgium.
Intel technology industry leader
In September 2007, Intel led the industry to exhibit the 32nm process test silicon wafers for the first time at the Developer Forum. The silicon wafer is used to test device performance and test the new process is reasonable, not the actual logic circuit. In general, only the production of practical SRAM (Static Random Access Memory) devices can represent the basic maturity of the process. In accordance with Intel's "pendulum strategy," in 2009 they will introduce a 32-nanometer microprocessor and put it into mass production. The microprocessor was developed under the code name Westmere.
Intel is characterized by the development of state-of-the-art 32-nm processes with strong research funding. The first generation of 32nm technology developed by Intel in 2007 is mainly based on the high dielectric constant insulating layer process and metal gate technology used at high temperatures.
In 2008, Intel developed the second generation of high dielectric dielectric/metal gate technology for 32nm processes. Intel, the first in the industry to mass produce high dielectric dielectric/metal gate chips, has developed a new process for forming gates after high temperature annealing, avoiding the effects of high temperatures on the gate. Chips made with the second-generation 32-nanometer process can integrate 1.9 billion transistors. Intel's 32nm test chip is a logic integrated system chip and SRAM.
Participating in Intel's research and development is Micron Technology Inc., which has jointly developed multi-value NAND flash memory that successfully uses 34nm process technology. The products that have been mass-produced since the second half of 2008 are multi-value NAND flash memories with a capacity of 32 Gbit, which can be used for SSDs (Solid State Drives). According to Brian Shirley, vice president of Micron's memory division, the chip is "the highest density memory in the volume of products."
IBM camp is advancing by leaps and bounds
The IBM camp is characterized by the development of a common 32-nanometer technology based on fundamentally unchanged traditional processes. There are seven major semiconductor companies working with IBM to develop standard CMOS process technology at 32nm nodes: AMD, Freescale Semiconductor, Infineon, Samsung Electronics, STMicroelectronics, Singapore Chartered Semiconductor and Toshiba. Japan's NEC and Hitachi also joined the R&D team. After more than a year of collaborative development, in 2008, the IBM camp launched the "CommonPlat-form" 32nm bulk silicon CMOS general-purpose manufacturing platform. The general manufacturing platform uses a high dielectric gate dielectric and a metal gate. By using a high dielectric insulating dielectric material and a metal gate, device performance can be improved by about 35% and power consumption can be reduced by about 50%.
IBM engineers used a new process called "High-KGate-First". In the gate process, if a High-K/metal gate is used before the high temperature annealing process for forming the gate, the metal is affected by the high temperature, which causes a change in the gate operating parameters and deteriorates the transistor characteristics. The IBM camp has developed mass production technologies for both power-saving and high-speed 32-nm devices, and is confident that these standard process technologies will be extended to 22 nm. The processes developed by the IBM camp are as traditional as possible and do not add significant cost. In order to reduce costs, the power-saving type does not use the strained silicon technology with a slightly higher cost.
IBM's high-k/metal gates reduce the low-power oxide thickness by about 10 angstroms, resulting in an inversion layer thickness of 14 angstroms. The thinner gate oxide thickness improves performance by reducing the gate length to 30 nanometers while keeping the SRAM voltage minimum to an optimal level, allowing the contact holes to be closer together without worrying about short circuits. Danger.
In April 2008, IBM announced that it would allow customers to start designing at 32 nm. Since September 2008, IBM's 32nm universal manufacturing platform has officially started trial production. Successful SRAM, NOR and NAND flash and other logic circuits have been tried. The ARM processor core "Cortex-M3" was prototyped using IBM's 32nm low-power process. The prototype is called "Cassini". The 32nm process based on the common platform will be mass-produced from the end of 2009.
In October 2008, IBM and the UK ARM adopted the IBM camp's bulk silicon CMOS general-purpose manufacturing platform "CommonPlatform" to jointly develop optimized physical IP for 32nm and 28nm processes. They are working at 32nm. At the same time as the development of 28nm process technology, the device layout is the optimized layout of physical IP. In this way, the advantages of the manufacturing process can be fully utilized to improve the quality and reliability of the device.
In addition, ARM's physical IP business competitor - the US Virag eL ogic company also released a 32-nanometer commercial physical IP specialization technology in the United States in October 2008.
The author believes that in the context of this global financial crisis, IBM and other companies are strongly encouraged to develop a new generation of cutting-edge processes and technologies based on the basic use of traditional chip technology. Especially when it is impossible to implement on hardware, give full play to the advantages of software technology, and combine soft and hard to open up new development paths. The practice of IBM and other companies shows that through the combination of strengths and weaknesses, the combination of software and hardware can fully exploit the potential of existing equipment and technology. This is a broad road to the development of advanced technologies under the current situation.
TSMC focuses on low-cost processes
TSMC has developed a 32nm technology that does not require high dielectric gate dielectrics and metal gates. This low-cost 32-nm process uses SiON gate dielectrics used in the 45-nm process. It can be used to produce integrated system chips for analog and digital. On this basis, in October 2008, TSMC announced its 28-nm process, which has SiON gate dielectric technology for low-power integrated systems and high-k dielectric gate insulation for high-function integrated systems. Two kinds of dielectric/metal gate technology. The low-power type is suitable for baseband LSI and application processors for mobile phones. Compared with the company's 40nm process low-power products, the gate density is doubled and the operating speed is increased by up to 50%. The power consumption can be reduced by 30%~50% under the same working speed. High function The type is suitable for manufacturing general-purpose devices such as microprocessors, graphics processors and FPGAs. Compared with the company's 40-nanometer high-performance model, the gate density is 2 times and the working speed is increased by more than 30% under the same power consumption. Participated in the research and development of TSMC, and has worked with Texas Instruments for many years.
It should be noted that the 32 nm node technology of SiON gate dielectric developed by TSMC can reduce the gate capacitance and reduce the power consumption of the device compared with the high dielectric gate dielectric/metal gate process, but its disadvantage is the device. The leakage current is not significantly reduced. TSMC believes that SiON gate dielectric technology has advantages over high-dielectric gate dielectric technology that reduces leakage current when it comes to applications that reduce operating power consumption, such as mobile phones.
At the technical seminar held in Yokohama in October 2008, TSMC announced that it is expected to use liquid-immersed ArF lithography in the 28-nanometer process, which is expected to begin mass production in early 2010.
Japanese companies focus on mass production
In addition, there are Japanese companies, limited to financial resources, they mainly develop mass production processes and Know-How at 32 nm nodes.
Selete (Semiconductor Advanced Technology), an advanced integrated circuit development organization composed of Japanese semiconductor manufacturers, has successfully developed a 32-nm large-scale integrated circuit manufacturing process. There are three main points: one is to develop a new type of electrode material for leakage prevention under the condition of finer line width; the other is to prevent the interlayer insulation material between the overlapping wiring layers; the third is to develop a new electrode material and accelerate Practical research on 32nm semiconductor technology.
A new anti-leakage electrode material is used to control the gate of the transistor. The gate material of a conventional transistor is made of polysilicon, and for the purpose of insulation, silicon oxide is used around the polysilicon. However, as the device is miniaturized, this causes a problem of excessive leakage current. To solve this problem, after testing a variety of materials, Selete and Hitachi determined to use TiN as the gate. Traditional integrated circuits are divided into pMOS and nMOS. It has been tested that TiN is suitable for both types of integrated circuits, that is, after using TiN, leakage current is effectively prevented.
The insulating material is Hf (Hafnium Silicate). For nMOS doped magnesium oxide, for pMOS doped alumina. If pMOS and nMOS use the same metal gate material, the process can be simplified and the manufacturing cost can be reduced. In addition, the 32nm device developed reduces the on and off voltage by 0.2 volts. Thus, the device can be expected to be suitable for high speed operation.
Waseda University and the Institute of Materials Research have jointly developed new materials for 32nm semiconductors. This material consists of an alloy and carbon that allows the device to operate stably and significantly reduce power consumption.
NEC Corporation has announced a wiring technology of a 32 nm process that realizes continuous film formation of any layer including an interlayer insulating film by lowering the dielectric constant of the interlayer insulating film.
Japan's Fujitsu has developed 32nm process CMOS technology that does not use metal gate materials, which can reduce production costs.
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22nm process has achieved breakthrough
As the IBM camp has concentrated on the world's major semiconductor companies, through cooperation, the development of 22nm process is progressing rapidly. In August 2008, they first released a 22nm SRAM chip that was successfully produced in the Albany Nanotechnology Laboratory in the United States. The process technology has the following seven characteristics: high dielectric gate insulating layer/metal gate, transistor with gate length less than 25 nm, thin isolation layer, new ion implantation method, tip annealing technology, ultra-thin silicide, Inlaid with Cu contacts. The chip lithography uses high numerical aperture (high-NA) immersion lithography.
It is particularly worth noting that, like the 32nm process, the 22nm process of the IBM camp does not make major changes to the traditional chip process. This not only reduces the technical difficulty, but also significantly reduces production costs. Based on this, the IBM camp recently announced that it is ahead of Intel in the 22nm process.
Experts pointed out that the difficulty in restricting the progress of micro-processes of chips is mainly lithography. The new generation of lithography is technically demanding, and the cost of manufacturing equipment is extremely high, and most companies cannot afford it alone. IBM's 22nm process is mainly a major breakthrough in lithography. It uses MentorGraphics's computational microlithography technology, which uses existing microlithography tools and is produced by a large number of parallel calculations. The current equipment can be improved to complete the lithography of 22nm chips. Computation of microlithography is a new technical idea and attempt. The core is to optimize the entire process design with software.
There are three camps for the development of microchip technology for 32nm chips worldwide. The largest number of participating companies is the IBM camp, followed by Intel Corporation, and the third is Japanese companies. In addition, TSMC in Taiwan and IMEC in Europe and Belgium.
Intel technology industry leader
In September 2007, Intel led the industry to exhibit the 32nm process test silicon wafers for the first time at the Developer Forum. The silicon wafer is used to test device performance and test the new process is reasonable, not the actual logic circuit. In general, only the production of practical SRAM (Static Random Access Memory) devices can represent the basic maturity of the process. In accordance with Intel's "pendulum strategy," in 2009 they will introduce a 32-nanometer microprocessor and put it into mass production. The microprocessor was developed under the code name Westmere.
Intel is characterized by the development of state-of-the-art 32-nm processes with strong research funding. The first generation of 32nm technology developed by Intel in 2007 is mainly based on the high dielectric constant insulating layer process and metal gate technology used at high temperatures.
In 2008, Intel developed the second generation of high dielectric dielectric/metal gate technology for 32nm processes. Intel, the first in the industry to mass produce high dielectric dielectric/metal gate chips, has developed a new process for forming gates after high temperature annealing, avoiding the effects of high temperatures on the gate. Chips made with the second-generation 32-nanometer process can integrate 1.9 billion transistors. Intel's 32nm test chip is a logic integrated system chip and SRAM.
Participating in Intel's research and development is Micron Technology Inc., which has jointly developed multi-value NAND flash memory that successfully uses 34nm process technology. The products that have been mass-produced since the second half of 2008 are multi-value NAND flash memories with a capacity of 32 Gbit, which can be used for SSDs (Solid State Drives). According to Brian Shirley, vice president of Micron's memory division, the chip is "the highest density memory in the volume of products."
IBM camp is advancing by leaps and bounds
The IBM camp is characterized by the development of a common 32-nanometer technology based on fundamentally unchanged traditional processes. There are seven major semiconductor companies working with IBM to develop standard CMOS process technology at 32nm nodes: AMD, Freescale Semiconductor, Infineon, Samsung Electronics, STMicroelectronics, Singapore Chartered Semiconductor and Toshiba. Japan's NEC and Hitachi also joined the R&D team. After more than a year of collaborative development, in 2008, the IBM camp launched the "CommonPlat-form" 32nm bulk silicon CMOS general-purpose manufacturing platform. The general manufacturing platform uses a high dielectric gate dielectric and a metal gate. By using a high dielectric insulating dielectric material and a metal gate, device performance can be improved by about 35% and power consumption can be reduced by about 50%.
IBM engineers used a new process called "High-KGate-First". In the gate process, if a High-K/metal gate is used before the high temperature annealing process for forming the gate, the metal is affected by the high temperature, which causes a change in the gate operating parameters and deteriorates the transistor characteristics. The IBM camp has developed mass production technologies for both power-saving and high-speed 32-nm devices, and is confident that these standard process technologies will be extended to 22 nm. The processes developed by the IBM camp are as traditional as possible and do not add significant cost. In order to reduce costs, the power-saving type does not use the strained silicon technology with a slightly higher cost.
IBM's high-k/metal gates reduce the low-power oxide thickness by about 10 angstroms, resulting in an inversion layer thickness of 14 angstroms. The thinner gate oxide thickness improves performance by reducing the gate length to 30 nanometers while keeping the SRAM voltage minimum to an optimal level, allowing the contact holes to be closer together without worrying about short circuits. Danger.
In April 2008, IBM announced that it would allow customers to start designing at 32 nm. Since September 2008, IBM's 32nm universal manufacturing platform has officially started trial production. Successful SRAM, NOR and NAND flash and other logic circuits have been tried. The ARM processor core "Cortex-M3" was prototyped using IBM's 32nm low-power process. The prototype is called "Cassini". The 32nm process based on the common platform will be mass-produced from the end of 2009.
In October 2008, IBM and the UK ARM adopted the IBM camp's bulk silicon CMOS general-purpose manufacturing platform "CommonPlatform" to jointly develop optimized physical IP for 32nm and 28nm processes. They are working at 32nm. At the same time as the development of 28nm process technology, the device layout is the optimized layout of physical IP. In this way, the advantages of the manufacturing process can be fully utilized to improve the quality and reliability of the device.
In addition, ARM's physical IP business competitor - the US Virag eL ogic company also released a 32-nanometer commercial physical IP specialization technology in the United States in October 2008.
The author believes that in the context of this global financial crisis, IBM and other companies are strongly encouraged to develop a new generation of cutting-edge processes and technologies based on the basic use of traditional chip technology. Especially when it is impossible to implement on hardware, give full play to the advantages of software technology, and combine soft and hard to open up new development paths. The practice of IBM and other companies shows that through the combination of strengths and weaknesses, the combination of software and hardware can fully exploit the potential of existing equipment and technology. This is a broad road to the development of advanced technologies under the current situation.
TSMC focuses on low-cost processes
TSMC has developed a 32nm technology that does not require high dielectric gate dielectrics and metal gates. This low-cost 32-nm process uses SiON gate dielectrics used in the 45-nm process. It can be used to produce integrated system chips for analog and digital. On this basis, in October 2008, TSMC announced its 28-nm process, which has SiON gate dielectric technology for low-power integrated systems and high-k dielectric gate insulation for high-function integrated systems. Two kinds of dielectric/metal gate technology. The low-power type is suitable for baseband LSI and application processors for mobile phones. Compared with the company's 40nm process low-power products, the gate density is doubled and the operating speed is increased by up to 50%. The power consumption can be reduced by 30%~50% under the same working speed. High function The type is suitable for manufacturing general-purpose devices such as microprocessors, graphics processors and FPGAs. Compared with the company's 40-nanometer high-performance model, the gate density is 2 times and the working speed is increased by more than 30% under the same power consumption. Participated in the research and development of TSMC, and has worked with Texas Instruments for many years.
It should be noted that the 32 nm node technology of SiON gate dielectric developed by TSMC can reduce the gate capacitance and reduce the power consumption of the device compared with the high dielectric gate dielectric/metal gate process, but its disadvantage is the device. The leakage current is not significantly reduced. TSMC believes that SiON gate dielectric technology has advantages over high-dielectric gate dielectric technology that reduces leakage current when it comes to applications that reduce operating power consumption, such as mobile phones.
At the technical seminar held in Yokohama in October 2008, TSMC announced that it is expected to use liquid-immersed ArF lithography in the 28-nanometer process, which is expected to begin mass production in early 2010.
Japanese companies focus on mass production
In addition, there are Japanese companies, limited to financial resources, they mainly develop mass production processes and Know-How at 32 nm nodes.
Selete (Semiconductor Advanced Technology), an advanced integrated circuit development organization composed of Japanese semiconductor manufacturers, has successfully developed a 32-nm large-scale integrated circuit manufacturing process. There are three main points: one is to develop a new type of electrode material for leakage prevention under the condition of finer line width; the other is to prevent the interlayer insulation material between the overlapping wiring layers; the third is to develop a new electrode material and accelerate Practical research on 32nm semiconductor technology.
A new anti-leakage electrode material is used to control the gate of the transistor. The gate material of a conventional transistor is made of polysilicon, and for the purpose of insulation, silicon oxide is used around the polysilicon. However, as the device is miniaturized, this causes a problem of excessive leakage current. To solve this problem, after testing a variety of materials, Selete and Hitachi determined to use TiN as the gate. Traditional integrated circuits are divided into pMOS and nMOS. It has been tested that TiN is suitable for both types of integrated circuits, that is, after using TiN, leakage current is effectively prevented.
The insulating material is Hf (Hafnium Silicate). For nMOS doped magnesium oxide, for pMOS doped alumina. If pMOS and nMOS use the same metal gate material, the process can be simplified and the manufacturing cost can be reduced. In addition, the 32nm device developed reduces the on and off voltage by 0.2 volts. Thus, the device can be expected to be suitable for high speed operation.
Waseda University and the Institute of Materials Research have jointly developed new materials for 32nm semiconductors. This material consists of an alloy and carbon that allows the device to operate stably and significantly reduce power consumption.
NEC Corporation has announced a wiring technology of a 32 nm process that realizes continuous film formation of any layer including an interlayer insulating film by lowering the dielectric constant of the interlayer insulating film.
Japan's Fujitsu has developed 32nm process CMOS technology that does not use metal gate materials, which can reduce production costs.
Related Links
22nm process has achieved breakthrough
As the IBM camp has concentrated on the world's major semiconductor companies, through cooperation, the development of 22nm process is progressing rapidly. In August 2008, they first released a 22nm SRAM chip that was successfully produced in the Albany Nanotechnology Laboratory in the United States. The process technology has the following seven characteristics: high dielectric gate insulating layer/metal gate, transistor with gate length less than 25 nm, thin isolation layer, new ion implantation method, tip annealing technology, ultra-thin silicide, Inlaid with Cu contacts. The chip lithography uses high numerical aperture (high-NA) immersion lithography.
It is particularly worth noting that, like the 32nm process, the 22nm process of the IBM camp does not make major changes to the traditional chip process. This not only reduces the technical difficulty, but also significantly reduces production costs. Based on this, the IBM camp recently announced that it is ahead of Intel in the 22nm process.
Experts pointed out that the difficulty in restricting the progress of micro-processes of chips is mainly lithography. The new generation of lithography is technically demanding, and the cost of manufacturing equipment is extremely high, and most companies cannot afford it alone. IBM's 22nm process is mainly a major breakthrough in lithography. It uses MentorGraphics's computational microlithography technology, which uses existing microlithography tools and is produced by a large number of parallel calculations. The current equipment can be improved to complete the lithography of 22nm chips. Computation of microlithography is a new technical idea and attempt. The core is to optimize the entire process design with software.
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