Fine analysis of the current flowing out of the source of the flyback switching MOSFET
Analysis of the turning point of the current (Is) waveform from the source of the flyback switching MOSFET .
Many engineers in the power development and debugging process, some of the key points of the measured waveform is not very clear, the following analysis of the measured waveform of the flyback power supply.
Problem 1, a flyback power supply measured Ids current when there is a spike at the front end (as shown in the red circle in the figure below), what is the cause of this spike? How to eliminate or improve?
Everyone knows that this spike occurs when the switch MOS is turned on. According to the flyback loop, the Ids current loop is Vbus through the primary side of the transformer, and then through the MOS to Vbus to form a loop. Originally, the inductance of the primary side coil, its current can not be abrupt, it should rise linearly, but due to the distributed capacitance between the turns of the primary side coil (C in the figure below), at the instant of opening, Vbus is divided into capacitor C to MOS. There is a high frequency path, so a very short spike is formed.
After analysis, it is known that the peak current is caused by the distribution parameter of the primary side of the transformer. Therefore, it is necessary to start from the original winding layer and the fingertip of the layer, and the gap can be increased to reduce the coupling, and the single layer winding can be designed as much as possible.
For example, the transformer should use a large Ae value, which reduces the number of winding turns in the design and reduces the number of layers, thereby making the interlayer capacitance smaller. It can also reduce the contact surface between the wires to reduce the distributed capacitance. For example, the sandwich winding method separates the primary side to improve the peak and reduces the leakage. Of course, the presence of distributed capacitance cannot be completely avoided in any way, so this spike cannot be completely eliminated. And the oscillation caused by this high peak is not good for EMI, and the actual work impact is not big. However, if it is too high, it may cause the chip overcurrent detection to be triggered by mistake.
Therefore, the power IC will add a 200nS-500nS LEB Time to prevent false triggering, which is what we often say.
Problem 2: When switching the MOS off terminal, there is a depression on the IS current waveform (the current waveform in the red circle as shown below). What is going on? How to improve?
Before saying this reason, compare the waveforms of the mos drain current Id and the mos source current Is.
The measured Id waveform is as follows
The measured Is waveform is as follows
As you can see from the above two figures, what is the ID bigger than IS? In fact, Is is not equal to Id, Is = Id + Igs (Igs is negative current here, Cgs discharge current is shown below), then A, B two-point waveform, it is easy to explain.
Id is larger than Is because IS is superimposed with a reverse current, so the Is drop inflection point occurs. Obviously to improve this current sink can be adjusted by switching the MOS transistor model.
After reading the current waveform of Id above, the problem comes again. Why does the current of ID appear negative when mos is turned off? As shown below
When the MOS is turned off, the leakage inductance energy flows out to the Coss to the high point, which is the apex of the Vds reflection peak. After the highest point, the Lk phase is inverted, and the Coss is reversely discharged. At this time, the current flows out, that is, the negative current portion of the Id is generated.
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